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march 2012 ? 2011 fairchild semiconductor corporation www.fairchildsemi.com FDMF6706C ? rev. 1.0 2 FDMF6706C - extra-small high-perfo rmance, high-frequency drmos module FDMF6706C ? extra-small, high-performance, high- frequency drmos module benefits ? ultra-compact 6x6mm pqfn, 72% space-saving compared to conventional discrete solutions ? fully optimized system efficiency ? clean switching waveforms with minimal ringing ? high-current handling features ? over 93% peak-efficiency ? high-current handling of 43a ? high-performance pqfn copper clip package ? 3-state 5v pwm input driver ? shorter propagation delays than fdmf6704 ? shorter dead times than fdmf6704 ? skip-mode smod# (low-side gate turn off) input ? thermal warning flag for over-temperature condition ? driver output disable function (disb# pin) ? internal pull-up and pull-down for smod# and disb# inputs, respectively ? fairchild powertrench? technology mosfets for clean voltage waveforms and reduced ringing ? fairchild syncfet? (integrated schottky diode) technology in the low-side mosfet ? integrated bootstrap schottky diode ? adaptive gate drive timing for shoot-through protection ? under-voltage lockout (uvlo) ? optimized for switching frequencies up to 1mhz ? low-profile smd package ? fairchild green packaging and rohs compliant ? based on the intel? 4.0 drmos standard description the xs? drmos family is fairchild?s next-generation, fully optimized, ultra-compact, integrated mosfet plus driver power stage solutions for high-current, high- frequency, synchronous buck dc-dc applications. the FDMF6706C integrates a driver ic, two power mosfets, and a bootstrap schottky diode into a thermally enhanced, ultra-compact 6x6mm pqfn package. with an integrated approach, the complete switching power stage is optimized with regards to driver and mosfet dynamic performance, system inductance, and power mosfet r ds(on) . xs? drmos uses fairchild's high-performanc e powertrench? mosfet technology, which dramatically reduces switch ringing, eliminating the need for a snubber circuit in most buck converter applications. a new driver ic with reduced dead times and propagation delays further enhances the performance of this part. a thermal warning function has been included to warn of a potential over-temperature situation. the FDMF6706C also incorporates features, such as skip mode (smod), for improved light-load efficiency along with a 3-state 5v pwm input for compatibility with a wide range of pwm controllers. applications ? high-performance gaming motherboards ? compact blade servers, v-core and non-v-core dc-dc converters ? desktop computers, v-core and non-v-core dc-dc converters ? workstations ? high-current dc-dc point-of-load (pol) converters ? networking and telecom microprocessor voltage regulators ? small form-factor voltage regulator modules ordering information part number current rating input voltage switching frequency package top mark FDMF6706C 40a 12v 1000khz 40-lead, clipbond pqfn drmos, 6.0x6.0mm package FDMF6706C
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FDMF6706C ? rev. 1.0.2 2 FDMF6706C - extra-small high-perfo rmance, high-frequency drmos module typical application circuit figure 1. typical application circuit drmos block diagram figure 2. drmos block diagram smod# pwm vcin vdrv vin pgnd phase gh d boot boot gl cgnd disb# thwn# q1 hs power mosfet input 3- state logic r up_pwm v cin v cin uvlo gh logic level shift dead-time control temp. sense 30k 30k gl logic 10 a 10 a r dn_pwm q2 ls power mosfet vswh v drv v out pwm input vdrv vcin vin pwm disb# off on c vdrv c vin c boot r boot l out c out thwn# boot cgnd pgnd disb# FDMF6706C smod# open drain output phase v 5v vswh v in 3v ~ 15v
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FDMF6706C ? rev. 1.0.2 3 FDMF6706C - extra-small high-perfo rmance, high-frequency drmos module pin configuration figure 3. bottom view figure 4. top view pin definitions pin # name description 1 smod# when smod#=high, the low-side driver is the inverse of pwm input. when smod#=low, the low-side driver is disabled. this pin has a 10 a internal pull-up current source. do not add a noise filter capacitor. 2 vcin ic bias supply. minimum 1f ceramic capacitor is recommended from this pin to cgnd. 3 vdrv power for gate driver. minimum 1f ceramic capacitor is recommended to be connected as close as possible from this pin to cgnd. 4 boot bootstrap supply input. provides voltage supp ly to high-side mosfet driver. connect bootstrap capacitor from this pin to phase. 5, 37, 41 cgnd ic ground. ground return for driver ic. 6 gh for manufacturing test only. this pin must float. must not be connected to any pin. 7 phase switch node pin for bootstrap capacitor rout ing. electrically shorted to vswh pin. 8 nc no connect. the pin is not electrically connec ted internally, but can be connected to vin for convenience. 9 - 14, 42 vin power input. output stage supply voltage. 15, 29 - 35, 43 vswh switch node input. provides return for high-side bootstrapped driver and acts as a sense point for the adaptive shoot-through protection. 16 ? 28 pgnd power ground. output stage ground. source pin of low-side mosfet. 36 gl for manufacturing test only. this pin must float. must not be connected to any pin. 38 thwn# thermal warning flag, open collector output. when temperature exceeds the trip limit, the output is pulled low. thwn# does not disable the module. 39 disb# output disable. when low, this pin disables power mosfet switching (gh and gl are held low). this pin has a 10a internal pull-down current source. do not add a noise filter capacitor. 40 pwm pwm signal input. this pin accepts a 3-state 5v pwm signal from the controller.
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FDMF6706C ? rev. 1.0.2 4 FDMF6706C - extra-small high-perfo rmance, high-frequency drmos module absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating conditions and st ressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit vcin, vdrv, disb#, pwm, smod#, gl, thwn# to cgnd pins 6 v vin to pgnd, cgnd pins 25 boot, gh to vswh , phase pins 6 vswh, phase to pgnd, cgnd pins 25 boot to pgnd, cgnd pins 27 boot to vdrv 22 i o(av) (1) v in =12v, v o =1.0v f sw =300khz 43 a f sw =1mhz 40 jpcb junction-to-pcb thermal resistance 3.5 c/w t stg operating and storage temperature range -55 +150 c esd electrostatic discharge protection human body model, jesd22-a114 2000 v charged device model, jesd22-c101 2000 note: 1. i o(av) is rated using fairchild?s drmos evaluation board, at t a = 25c, with natural convection cooling. this rating is limited by the peak drmos temperature, t j = 150c, and varies depending on operating conditions and pcb layout. this rating can be changed with different application settings . recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter min. typ. max. unit v cin control circuit supply voltage 4.5 5.0 5.5 v v drv gate drive circuit supply voltage 4.5 5.0 5.5 v v in output stage supply voltage (2) 3.0 12.0 15.0 v note: 2. operating at high v in can create excessive ac overshoots on the vswh-to-gnd and boot-to-gnd nodes during mosfet switching transients. for reliable drmos operation, vswh-to-gnd and boot-to-gnd must remain at or below the absolute maximum ratings shown in the table above. refer to the ?application information? and ?pcb layou t guidelines? sections of this da tasheet for additi onal information .
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FDMF6706C ? rev. 1.0.2 5 FDMF6706C - extra-small high-perfo rmance, high-frequency drmos module electrical characteristics typical values are v in = 12v, v cin = 5v, v drv = 5v, and t a = +25c unless otherwise noted. symbol parameter condition min. typ. max. unit basic operation i q quiescent current i q =i vcin +i vdrv , pwm=low or high or float 2 ma uvlo uvlo threshold v cin rising 2.9 3.1 3.3 v uvlo _hyst uvlo hysteresis 0.4 v pwm input r up_pwm pull-up impedance 10 k ? r dn_pwm pull-down impedance 10 k ? v ih_pwm pwm high level voltage 3.30 3.55 3.80 v v tri_hi 3-state rising threshold 3.20 3.45 3.70 v v tri_lo 3-state falling threshold 1.00 1.25 1.50 v v il_pwm pwm low level voltage 0.85 1.15 1.40 v t d_hold-off 3-state shutoff time 160 200 ns v hiz_pwm 3-state open voltage 2.3 2.5 2.7 v disb# input v ih_disb high-level input voltage 2 v v il_disb low-level input voltage 0.8 v i pld pull-down current 10 a t pd_disbl propagation delay pwm=gnd, delay between disb# from high to low to gl from high to low 25 ns t pd_disbh propagation delay pwm=gnd, delay between disb# from low to high to gl from low to high 25 ns smod# input v ih_smod high-level input voltage 2 v v il_smod low-level input voltage 0.8 v i plm pull-up current 10 a t pd_slgll propagation delay pwm=gnd, delay between smod# from high to low to gl from high to low 10 ns t pd_shglh propagation delay pwm=gnd, delay between smod# from low to high to gl from low to high 10 ns thermal warning flag t act activation temperature 150 c t rst reset temperature 135 c r thwn pull-down resistance i pld =5ma 30 ? 250ns timeout circuit t d_timeout timeout delay sw=0v, delay between gh from high to low and gl from low to high 250 ns continued on the following page?
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FDMF6706C ? rev. 1.0.2 6 FDMF6706C - extra-small high-perfo rmance, high-frequency drmos module electrical characteristics typical values are v in = 12v, v cin = 5v, v drv = 5v, and t a = +25c unless otherwise noted. symbol parameter condition min. typ. max. unit high-side driver r source_gh output impedance, sourcing source current=100ma 1 ? r sink_gh output impedance, sinking sink current=100ma 0.8 ? t r_gh rise time gh=10% to 90%, c load =1.1nf 12 ns t f_gh fall time gh=90% to 10%, c load =1.1nf 11 ns t d_deadon ls to hs deadband time gl going low to gh going high, 2v gl to 10 % gh 10 ns t pd_plghl pwm low propagation delay pwm going low to gh going low, v il_pwm to 90% gh 16 30 ns t pd_phghh pwm high propagation delay (smod held low) pwm going high to gh going high, v ih_pwm to 10% gh (smod=low) 30 ns t pd_tsghh exiting 3-state propagation delay pwm (from 3-state) going high to gh going high, v ih_pwm to 10% gh 30 ns low-side driver r source_gl output impedance, sourcing source current=100ma 1 ? r sink_gl output impedance, sinking sink current=100ma 0.5 ? t r_gl rise time gl=10% to 90%, c load =2.7nf 12 ns t f_gl fall time gl=90% to 10%, c load =2.7nf 8 ns t d_deadoff hs to ls deadband time sw going low to gl going high, 2.2v sw to 10% gl 12 ns t pd_phgll pwm-high propagation delay pwm going high to gl going low, v ih_pwm to 90% gl 9 25 ns t pd_tsglh exiting 3-state propagation delay pwm (from 3-state) going low to gl going high, v il_pwm to 10% gl 20 ns boot diode v f forward-voltage drop i f =10ma 0.35 v v r breakdown voltage i r =1ma 22 v
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FDMF6706C ? rev. 1.0.2 7 FDMF6706C - extra-small high-perfo rmance, high-frequency drmos module figure 5. pwm timing diagram t d_deadon pwm vswh gh to v s w h gl t pd phgll t d_deadoff v ih _ pwm v il _ pwm 90% 90% 2.0v 10% t pd plghl 2.2v 10% t d _ timeout ( 250ns timeout) 1.2v
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FDMF6706C ? rev. 1.0.2 8 FDMF6706C - extra-small high-performance, high- frequency drmos module typical performance characteristics test conditions: v in =12v, v out =1.0v, v cin =5v, v drv =5v, l out =320nh, t a =25c, and natural convection cooling, unless otherwise specified. figure 6. safe operating area figure 7. module power loss vs. output current figure 8. power loss vs. switching frequency figure 9. power loss vs. input voltage figure 10. power loss vs. driver supply voltage figure 11. power loss vs. output voltage 300khz 1mhz i out = 30a f sw = 300khz i out = 30a f sw = 300khz i out = 30a f sw = 300khz i out = 30a
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FDMF6706C ? rev. 1.0.2 9 FDMF6706C - extra-small high-perfo rmance, high-frequency drmos module typical performance characteristics (continued) test conditions: v in =12v, v out =1.0v, v cin =5v, v drv =5v, l out =320nh, t a =25c, and natural convection cooling, unless otherwise specified. figure 12. power loss vs. output inductance fi gure 13. driver supply current vs. frequency figure 14. driver supply current vs. driver supply voltage figure 15. driver supply current vs. output current figure 16. pwm thresholds vs. temperature figure 17. disb# thresholds vs. temperature f sw = 300khz i out = 0a f sw = 300khz i out = 30a i out = 0a
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FDMF6706C ? rev. 1.0.2 10 FDMF6706C - extra-small high-perfo rmance, high-frequency drmos module typical performance characteristics (continued) test conditions: v in =12v, v out =1.0v, v cin =5v, v drv =5v, l out =320nh, t a =25c, and natural convection cooling, unless otherwise specified. figure 18. smod# thresholds vs. te mperature figure 19. boot diode v f vs. temperature
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FDMF6706C ? rev. 1.0.2 11 FDMF6706C - extra-small high-perfo rmance, high-frequency drmos module functional description the FDMF6706C is a driver-plus-fet module optimized for the synchronous buck converter topology. a single pwm input signal is all that is required to properly drive the high-side and the low-side mosfets. each part is capable of driving speeds up to 1mhz. vcin and disable the vcin pin is monitored by an under-voltage lockout (uvlo) circuit. when v cin rises above ~3.1v, the driver is enabled for operation. when v cin falls below ~2.7v, the driver is disabled (gh, gl=0). the driver can also be disabled by pulling the disb# pin low (disb# < v il_disb ), which holds both gl and gh low regardless of the pwm input state. the driver can be enabled by raising the disb# pin voltage high (disb# > v ih_disb ). table 1. uvlo and disable logic uvlo disb# driver state 0 x disabled (gh, gl=0) 1 0 disabled (gh, gl=0) 1 1 enabled ( see table 2 ) 1 open disabled (gh, gl=0) note: 3. disb# has an internal pull-down current source of 10a. thermal warning flag the FDMF6706C provides a thermal warning flag (thwn) to warn of over-temperature conditions. the thermal warning flag uses an open-drain output that pulls to cgnd when the activation temperature (150c) is reached. the thwn output returns to a high- impedance state once the temperature falls to the reset temperature (135c). for use, the thwn output requires a pull-up resistor, which can be connected to vcin. thwn does not disable the drmos module. figure 20. thwn operation 3-state pwm input the FDMF6706C incorporates a 3-state 5v pwm input gate drive design. the 3-state gate drive has both logic high level and low level, along with a 3-state shutdown window. when the pwm input signal enters and remains within the 3-state window for a defined hold-off time (t d_hold-off ), both gl and gh are pulled low. this feature enables the gate drive to shut down both high-and low-side mosfets to support features such as phase shedding, which is a common feature on multiphase voltage regulators. operation when exiting 3-state condition when exiting a valid 3-state condition, the FDMF6706C design follows the pwm input command. if the pwm input goes from 3-state to low, the low side mosfet is turned on. if the pwm input goes from 3-state to high, the high-side mosfet is turned on. this is illustrated in figure 21. the FDMF6706C design allows for short propagation delays when exiting the 3-state window ( see electrical characteristics ). low-side driver the low-side driver (gl) is designed to drive a ground- referenced low r ds(on) n-channel mosfet. the bias for gl is internally connected between vdrv and cgnd. when the driver is enab led, the driver's output is 180 out of phase with the pwm input. when the driver is disabled (disb#=0v), gl is held low. high-side driver the high-side driver is designed to drive a floating n- channel mosfet. the bias voltage for the high-side driver is developed by a bootstrap supply circuit, consisting of the internal schottky diode and external bootstrap capacitor (c boot ). during startup, vswh is held at pgnd, allowing c boot to charge to vdrv through the internal diode. when the pwm input goes high, gh begins to charge the gate of the high-side mosfet (q1). during this transition, the charge is removed from c boot and delivered to the gate of q1. as q1 turns on, v swh rises to v in , forcing the boot pin to v in + v boot , which provides sufficient v gs enhancement for q1. to complete the switching cycle, q1 is turned off by pulling gh to vswh. c boot is then recharged to vdrv when vswh falls to pgnd. gh output is in- phase with the pwm input. the high-side gate is held low when the driver is disabled or the pwm signal is held within the 3-state window for longer than the 3- state hold-off time, t d_hold-off . 150c a ctivation tem p erature t j_driver ic thermal warning normal operation high low thwn logic state 135c rese t temperature
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FDMF6706C ? rev. 1.0.2 12 FDMF6706C - extra-small high-perfo rmance, high-frequency drmos module adaptive gate drive circuit the driver ic advanced design ensures minimum mosfet dead-time while eliminating potential shoot through (cross-conduction) currents. it senses the state of the mosfets and adjusts the gate drive adaptively to ensure they do not conduct simultaneously. figure 21 provides the relevant timing waveforms. to prevent overlap during the low-to-high switching transition (q2 off to q1 on), the adaptive circuitry monitors the voltage at the gl pin. when the pwm signal goes high, q2 begins to turn off after some propagation delay (t pd_phgll ). once the gl pin is discharged below ~2v, q1 begins to turn on after adaptive delay t d_deadon . to preclude overlap during the high-to-low transition (q1 off to q2 on), the adaptive circuitry monitors the voltage at the vswh pin. when the pwm signal goes low, q1 begins to turn off after some propagation delay (t pd_plghl ). once the vswh pin falls below ~2.2v, q2 begins to turn on after adaptive delay t d_deadoff . additionally, v gs(q1) is monitored. when v gs(q1) is discharged below ~1.2v, a secondary adaptive delay is initiated, which results in q2 being driven on after t d_timeout , regardless of sw state. this function is implemented to ensure c boot is recharged each switching cycle in the event that the sw voltage does not fall below the 2.2v adaptive threshold. secondary delay t d_timeout is longer than t d_deadoff . figure 21. pwm and 3-statetiming diagram notes: t pd_xxx = propagation delay from external signal (pwm, smod#, etc.) to ic generated signal. example (t pd_phgll ? pwm going high to ls v gs (gl) going low) t d_xxx = delay from ic generated signal to ic generated signal. example (t d_deadon ? ls v gs (gl) low to hs v gs (gh) high) pwm exiting 3-state t pd_phgll = pwm rise to ls v gs fall, v ih_pwm to 90% ls v gs t pd_tsghh = pwm 3-state to high to hs v gs rise, v ih_pwm to 10% hs v gs t pd_plghl = pwm fall to hs v gs fall, v il_pwm to 90% hs v gs t pd_tsglh = pwm 3-state to low to ls v gs rise, v il_pwm to 10% ls v gs t pd_phghh = pwm rise to hs v gs rise, v ih_pwm to 10% hs v gs (smod# held low) smod# dead times t pd_slgll = smod# fall to ls v gs fall, v il_smod to 90% ls v gs t d_deadon = ls v gs fall to hs v gs rise, ls-comp trip value (~2.0v gl) to 10% hs v gs t pd_shglh = smod# rise to ls v gs rise, v ih_smod to 10% ls v gs t d_deadoff = vswh fall to ls v gs rise, sw-comp trip value (~2.2v vswh) to 10% ls v gs t pd_tsghh vswh gh to vswh gl t pd_phgll t d_hold -off 90% less than t d_hold - off exit 3 s t a t e 2.0v pwm v il_pwm v ih_pwm v tri_hi v ih_pwm v ih_pwm 10% t r_gl t d_hold - off t pd_tsglh less than t d_hold - off exit 3-state v ih pwm v tri_hi v tri_lo v il_pwm t pd _ plghl t pd_tsghh dcm t f_gh t r_gh t d_hold - off 10% ccm dcm exit 3- state 90% 1 0% 90% enter 3 -state enter 3 -state t d_deadoff t d_deadon enter 3 - state t f_gl v in v out 2.2 v
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FDMF6706C ? rev. 1.0.2 13 FDMF6706C - extra-small high-perfo rmance, high-frequency drmos module skip mode (smod) the smod function allows for higher converter efficiency under light-load conditions. during smod, the low-side fet gate signal is disabled (held low), preventing discharging of the output capacitors as the filter inductor current attempts reverse current flow ? also known as ?diode emulation? mode. when the smod pin is pulled high, the synchronous buck converter works in synchronous mode, gating on the low-side fet. when the smod pin is pulled low, the low-side fet is gated off. the smod pin is connected to the pwm controller, which enables or disables the smod automatically when the controller detects light-load condition from output current sensing. normally this pin is active low. see figure 22 for timing delays . table 2. smod logic disb# pwm smod# gh gl 0 x x 0 0 1 3-state x 0 0 1 0 0 0 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 0 note: 4. the smod feature is intended to have low propagation delay between the smod signal and the low-side fet vgs resp onse time to control diode emulation on a cycle-by-cycle basis. figure 22. smod timing diagram t d_deadon pwm v swh gh to v swh gl t pd_phgll t pd_plghl t d_deadoff v ih_pwm v il_pwm 90% 10% 90% 2.0v 2.2v t pd_phghh t pd_shglh delay from smod# going high to ls v gs high hs turn -on with smod# low smod # t pd_slgll delay from smod# going low to ls v gs low dcm ccm ccm 10% v ih_pwm 10% v out v ih_smod v il_smod 10%
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FDMF6706C ? rev. 1.0.2 14 FDMF6706C - extra-small high-perfo rmance, high-frequency drmos module application information supply capacitor selection for the supply input (v cin ), a local ceramic bypass capacitor is recommended to reduce noise and to supply the peak current. use at least a 1f x7r or x5r capacitor. keep this capacitor close to the vcin pin and connect it to the gnd plane with vias. bootstrap circuit the bootstrap circuit uses a charge storage capacitor (c boot ), as shown in figure 23. a bootstrap capacitance of 100nf x7r or x5r capacitor is adequate. a series bootstrap resistor would be needed for specific applications to improve switching noise immunity. vcin filter the vdrv pin provides powe r to the gate drive of the high-side and low-side power fet. in most cases, it can be connected directly to vcin, the pin that provides power to the logic section of the driver. for additional noise immunity, an rc filter can be inserted between vdrv and vcin. recommended values would be 10 ? and 1f. power loss and efficiency measurement and calculation refer to figure 23 for power loss testing method. power loss calculations are: p in =(v in x i in ) + (v 5v x i 5v ) (w) p sw =v sw x i out (w) p out =v out x i out (w) p loss_module =p in - p sw (w) p loss_board =p in - p out (w) eff module =100 x p sw /p in (%) eff board =100 x p out /p in (%) figure 23. power loss measurement block diagram vdrv vcin vin pwm v 5v disb pwm input off on c vdr c vin c boot r boot l out c out a i 5v a i in v in vv sw a i out thwn boot vswh cgnd pgnd disb# FDMF6706C smod open- drain output phase v out
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FDMF6706C ? rev. 1.0.2 15 FDMF6706C - extra-small high-perfo rmance, high-frequency drmos module pcb layout guidelines figure 24 provides an example of a proper layout for the FDMF6706C and critical components. all of the high- current paths, such as v in , v swh , v out , and gnd copper, should be short and wide for low inductance and resistance. this technique aids in achieving a more stable and evenly distributed current flow, along with enhanced heat radiation and system performance. the following guidelines are recommendations for the pcb designer: 1. input ceramic bypass capacitors must be placed close to the vin and pgnd pins. this helps reduce the high-current power loop inductance and the input current ripple induced by the power mosfet switching operation. 2. the v swh copper trace serves two purposes. in addition to being the high-frequency current path from the drmos package to the output inductor, it also serves as a heat sink for the low-side mosfet in the drmos package. the trace should be short and wide enough to present a low- impedance path for the high-frequency, high- current flow between the drmos and inductor to minimize losses and temperature rise. note that the vswh node is a high voltage and high- frequency switching node with high noise potential. care should be taken to minimize coupling to adjacent traces. since this copper trace also acts as a heat sink for the lower fet, balance using the largest area possible to improve drmos cooling while maintaining acceptable noise emission. 3. an output inductor should be located close to the FDMF6706C to minimize the power loss due to the vswh copper trace. care should also be taken so the inductor dissipation does not heat the drmos. 4. powertrench? mosfets are used in the output stage. the power mosfets are effective at minimizing ringing due to fast switching. in most cases, no vswh snubber is required. if a snubber is used, it should be placed close to the vswh and pgnd pins. the resistor and capacitor need to be of proper size for the power dissipation. 5. vcin, vdrv, and boot capacitors should be placed as close as possible to the vcin to cgnd, vdrv to cgnd, and bo ot to phase pins to ensure clean and stable power. routing width and length should be considered as well. 6. include a trace from phase to vswh to improve noise margin. keep the trace as short as possible. 7. the layout should include the option to insert a small-value series boot resistor between the boot capacitor and boot pin. the boot-loop size, including r boot and c boot , should be as small as possible. the boot resistor is normally not required, but is effective at controlling the high- side mosfet turn-on slew rate. this can improve noise operating margin in synchronous buck designs that may have noise issues due to ground bounce or high positive and negative vswh ringing. inserting a boot resistance lowers the drmos efficiency. efficiency versus noise trade- offs must be considered. the vin and pgnd pins handle large current transients with frequency components greater than 100mhz. if possible, these pins should be connected directly to the vin and board gnd planes. the use of thermal relief traces in series with these pins is discouraged since this adds inductance to the power path. this added inductance in series with either the vin or pgnd pin degrades system noise immunity by increasing positive and negative vswh ringing. 8. cgnd pad and pgnd pins should be connected by plane gnd copper with multiple vias for stable grounding. poor grounding can create a noise transient offset voltage level between cgnd and pgnd. this could lead to faulty operation of gate driver and mosfet. 9. ringing at the boot pin is most effectively controlled by close placement of the boot capacitor. do not add an additional boot to the pgnd capacitor. this may lead to excess current flow through the boot diode. 10. the smod# and disb# pins have weak internal pull-up and pull-down current sources, respectively. these pins should not have any noise filter capacitors. do not to float these pins unless absolutely necessary. 11. use multiple vias on each copper area to interconnect top, inner, and bottom layers to help distribute current flow and heat conduction. vias should be relatively large and of reasonably low inductance. critical high-frequency components, such as r boot , c boot , the rc snubber, and bypass capacitors should be located as close to the respective drmos module pins as possible on the top layer of the pcb. if this is not feasible, they should be connected from the backside through a network of low-inductance vias.
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FDMF6706C ? rev. 1.0.2 16 FDMF6706C - extra-small high-perfo rmance, high-frequency drmos module figure 24. pcb layout example bottom view top view
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FDMF6706C ? rev. 1.0.2 17 FDMF6706C - extra-small high-perfo rmance, high-frequency drmos module physical dimensions figure 25. 40-lead, clipbond pqfn drmos, 6.0x6.0mm package package drawings are provided as a service to customers consi dering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packagi ng area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . bottom view land pattern recommendation notes: unless otherwise specified a) does not fully conform to jedec registration mo-220, dated may/2005. b) all dimensions are in millimeters. c) dimensions do not include burrs or mold flash. mold flash or burrs does not exceed 0.10mm. d) dimensioning and tolerancing per asme y14.5m-1994. e) drawing file name: pqfn40arev2 see detail 'a' detail 'a' scale: 2:1 seating plane 0.65 0.40 2.10 0.50 typ 4.50 5.80 2.50 0.25 1.60 0.60 0.15 2.10 0.35 1 top view front view c 0.30 0.20 0.05 0.00 1.10 0.90 0.10 c 0.08 c 10 11 20 21 30 31 40 0.40 0.50 (0.70) 0.40 2.000.10 2.000.10 (0.20) (0.20) 1.500.10 0.50 0.30 (40x) 0.20 6.00 6.00 0.10 c 2x b a 0.10 c 2x 0.30 0.20 (40x) 4.400.10 0.10 cab 0.05 c (2.20) 0.50 10 1 40 31 30 21 20 11 pin#1 indicator pin #1 indicator 2.400.10
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FDMF6706C ? rev. 1.0.2 18 FDMF6706C - extra-small high-perfo rmance, high-frequency drmos module

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